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A simple oxidation technique for quantum dot dimension shrinkage and tunnel barriers generation
(Elsevier B.V., 2007-05)
The tunnel barriers generation and the quantum dot size shrinkage play a significant role in single-electron transistor (SET) fabrication. Because the numerically etch indicators were not found, the technical indicators, ...
A systematic dry etching process for profile control of quantum dots and nanoconstrictions
(Elsevier B.V., 2007-08)
In essence, quantum dot dimensions and others can be laterally and vertically defined by using either bottom up or top down methods respectively. In fabrication that uses top down method, etch process hold a chief role. ...
Under Bump Metallurgy (UBM)-a technology review for flip chip packaging
(Department of Mechanical Engineering, University Malaya, 2007)
Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size ...
Effect of alignment mark architecture on alignment signal behavior in advanced lithography
(Universiti Malaya, 2007)
Alignment mark architecture is divided into two types, which depending on where the mark is defined. Alignment mark that is defined through the contact masking steps is known as contact mark and alignment mark that is ...
Nano patterning of cone dots and nano constrictions of negative e-beam resist for single electron transistor fabrication
(Springer New York, 2007-12)
We present an optimization of nano dot of negative tone e-beam resist which is a very important step in single electron transistor fabrication process. The optimum design of dot and nano constriction plays a significant ...
Designing of masks for quantum dot single electron transistor fabrication using E-beam nanolithography
(Nano Science and Technology Institute, 2007)
Quantum dot single electron transistor (QD SET) is able to be fabricated through a joint technique of e-beam lithography (EBL), pattern dependent oxidation (PADOX) and high density plasma etching. In this research, we have ...
Borophosphosilicate glass (BPSG) reflow characterization for submicron CMOS technology
(Universiti Kebangsaan Malaysia, 2007)
This paper involves the planarization of borophosphosilicate glass (BPSG) film using a new recipe for annealing process to improve the borophosphosilicate glass (BPSG) film flatness after reflow. This improvement is for ...
Semiconductor Nanowire
(Kementerian Pengajian Tinggi Malaysia (KPTM), 2007-08-10)
Semiconductor Nanowire represents an important and broad class of nanometer scale wire structure. Semiconductor Nanowire is a wire of dimension of the order of a nanometer or 10-9 meters. It is the one thousand times ...
An estimation of the energy and exergy efficiencies for the energy resources consumption in the transportation sector in Malaysia
(Elsevier Ltd., 2007-08)
The purpose of this work is to apply the useful energy and exergy analysis models for different modes of transport in Malaysia and to compare the result with a few countries. In this paper, energy and exergy efficiencies ...
Mask Making Process (Positive and Negative Mask)
(Kementerian Pengajian Tinggi Malaysia (KPTM), 2007-08-10)
Generally, two types of masks are used in MOSFET fabrication; positive mask and negative mask. These resists mask can be used either in lift off process or conventional lithography step depends on the fabrication process ...