Design and analysis of 90 nm two-stage operational amplifier using floating-gate MOSFET

Abstract

Low voltage, low power dissipation, high gain and matching are some of the concern when designing an analog circuit. A very low voltage can increase battery lifetime and integration density as market demands. Floating-gate Metal-Oxide-Semiconductor (MOS) also known as FGMOS is a new technology design that has been introduced as an element in low voltage circuit design in CMOS technology. FGMOS technique has been reported as low voltage and low power design application for increasing the battery lifetime due to its lower threshold voltage. The operational time of the FGMOS transistor can be improved by controlling the threshold voltage without reducing the feature size of the transistor. This research focuses on analyzing and comparing the simulation application of FGMOS technique with conventional MOSFET for various circuit designs. Capacitor ratio of 0.5 with value of 2 fF of the FGMOS transistor is chosen in order to have most stable output result. Proposed FGMOS operational amplifier circuit consists of two stages namely input differential circuit and output buffer stage that contributes in amplifying an input signal. The circuit simulations are analyzed using Full Custom Synopsys software with 90 nm CMOS technology. The simulated results show approximately 42 dB of gain with 3dBbandwidth of 233 kHz, unity gain bandwidth of 23.6 MHz and total power dissipation of 203.3520 mW. In conclusion, the proposed FGMOS designs show comparable result with conventional MOSFET designs. However, the proposed design performance can be improved in further research due to its lower threshold voltage.