Floating point multiplication unit using FPGA

Abstract

Field-programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combination functions such as decoders or simple mathematical functions. The architecture of floating point multiplication unit is designed using Cyclone FPGA chip. Floating point numbers are represented in IEEE 754 format which consists of 8 bits biased exponent, 23 bits fraction and sign bit. The suitability of FPGA as design platform is studied and performance of multiplication process is also observed for this project. Performance of multiplication process in various design aspects is done to achieve the objectives of this project. Design of architecture of floating point multiplication unit is done by using VHSIC hardware description language (VHDL) and Quartus II software using Altera UP3 Board which will be used as a simulation and synthesis tools. This project shows an example on how Floating Point Multiplication Unit Using FPGA is conducted using Quartus II software and VDHL.