Gate Oxide Integrity (GOI) Characterization For Deep Submicron CMOS Device

Abstract

Since the early days of Very Large Scale Integration (VLSI) era, the scaling of gate oxide thickness has been instrumental in controlling the short channel related effects in state-of-the-art device structure, as MOS gate dimensions have been scaled-down dramatically to a present day size of sub-0.1um channel length. This project studied the relationship between the gate oxide breakdowns phenomena with short channel related effects. Special attention was given to the carrier injections related oxide degradation which is Fowler-Nordheim (F-N) Tunneling, since this phenomenon was becoming profoundly important in ultra-thin gate oxide thickness. Standard gate oxide breakdown characterizations such as V-ramp test and substrate current measurement have been performed on MOS capacitor test structure of different sizes. Holes generation and trap mechanism is found to be one of the main cause for the intrinsic gate oxide breakdown. Other mechanism such as Wolter’s electron lattice damage might also be of a possible candidate, however further characterization such as Time Dependent Dielectric Breakdown (TDDB) Test is required to establish the relationship.