Now showing items 1-3 of 3

    • A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Rahman, A. A H; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin (Institute of Electrical and Electronics Engineering (IEEE), 2008-05)
      This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...
    • The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization 

      Hasliza, A. Rahim@Samsuddin; Rahman, A. A A; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin; Muhammad Imran, Ahmad (Institute of Electrical and Electronics Engineering (IEEE), 2008)
      Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important ...
    • Reduced complexity optimum detector for block data transmission systems 

      S. P. K., Babu; M. F. M., Salleh; Farid, Ghani (The Institute of Electronics, Information and Communication Engineers, 2009-12-10)
      Block Data Transmission Systems (BDTS) are used in high-speed wireless communication systems with time dispersive channel characteristics. In such systems, blocks of data are separated by zeros to mitigate the effect of ...