A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
Hasliza, A. Rahim@Samsuddin
Ab Rahman, A. A H
R. Badlishah, Ahmad
Wan Nur Suryani Firuz, Wan Ariffin
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This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three different types of genetic algorithms: simple genetic algorithm (SGA), steady-state algorithm (SSGA) and adaptive genetic algorithm (AGA) are employed in order to examine their performances in converging to their global minimums. Experimental results on Microelectronics Center of North Carolina (MCNC) benchmark problems show that the developed algorithm achieves an acceptable performance quality to the slicing floorplan. Furthermore, the robustness of genetic algorithm also has been investigated in order to validate the performance stability in achieving the optimal solution for every runtime. This algorithm demonstrates that SSGA converges to the optimal result faster than SGA and AGA. Besides that, SSGA also outperforms SGA and AGA in terms of robustness.
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The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization Hasliza, A. Rahim@Samsuddin; Rahman, A. A A; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin; Muhammad Imran, Ahmad (Institute of Electrical and Electronics Engineering (IEEE), 2008)Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important ...
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