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Borophosphosilicate glass (BPSG) reflow characterization for submicron CMOS technology
(Universiti Kebangsaan Malaysia, 2007)
This paper involves the planarization of borophosphosilicate glass (BPSG) film using a new recipe for annealing process to improve the borophosphosilicate glass (BPSG) film flatness after reflow. This improvement is for ...
Alignment mark architecture effect on alignment signal behavior in advanced lithography
(Institute of Electrical and Electronics Engineering (IEEE), 2006)
The downscaling of CMOS technology becomes a challenge to the scanner alignment system since overlay and alignment accuracy becomes tighter. Such a tight overlay requirement requires a very stable alignment performance. A ...