SOI Single-Electron Transistors (SET) design and process development

Abstract

Single-electron transistor (SET) is attractive devices to use for large-scale integration. SET can be made very small, dissipate little power, and can measure quantities of charge much faster than MOSFETs. This makes SET would replace field-effect transistor (FET). In this paper, Electron Beam (EBeam) GDS II Editor Software is utilized to design a mask for SOI SET fabrication. This system show promising result producing structure at nanometer scale node. Four masks step are involved namely source/drain & gate mask, Poly-Si gate electrode mask, contact mask, and metallization mask. SOI SET device design with a gate length and gate width of approximately 0.1μm and 0.02μm respectively is generated for fabrication process. In addition, the processes involve in SOI SET fabrication are also discussed.