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    SOI Single-Electron Transistors (SET) design and process development

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    SOI Single-Electron Transistors (SET) Design and Process Development.pdf (177.2Kb)
    Date
    2005-05-18
    Author
    Amiza, Rasmi
    Mohammad Nuzaihan, Md Nor
    Uda, Hashim
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    Abstract
    Single-electron transistor (SET) is attractive devices to use for large-scale integration. SET can be made very small, dissipate little power, and can measure quantities of charge much faster than MOSFETs. This makes SET would replace field-effect transistor (FET). In this paper, Electron Beam (EBeam) GDS II Editor Software is utilized to design a mask for SOI SET fabrication. This system show promising result producing structure at nanometer scale node. Four masks step are involved namely source/drain & gate mask, Poly-Si gate electrode mask, contact mask, and metallization mask. SOI SET device design with a gate length and gate width of approximately 0.1μm and 0.02μm respectively is generated for fabrication process. In addition, the processes involve in SOI SET fabrication are also discussed.
    URI
    http://dspace.unimap.edu.my/123456789/7104
    Collections
    • Conference Papers [2600]
    • Uda Hashim, Prof. Ts. Dr. [253]

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