Simulation for forming Shallow Trench Isolation in the IC using TCAD tools

Abstract

A simulation for forming shallow trench isolation (STI) in the integrated circuit (IC) is introduced. Firstly, using the Taurus Workbench-tools, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. The lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is formed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spinon-glass. Then curing at temperature above 800°C and etching back are performed with silicon nitride as end point.