Browsing School of Computer and Communication Engineering (FYP) by Author "Dr Phak LenEh Kan"
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Prototype of 16 BIT CPU on FPGA
Tamayanti, Ramasandram (Universiti Malaysia Perlis (UniMAP)School of Computer and Communication Engineering, 2015-06)This project is about Prototype of 16 bit CPU on FPGA. This prototyping of CPU uses the Very High Speed Integrated Circuit Hardware Description Language (VHDL) and the output will be displayed on the FPGA board. Few steps ...