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Design and analysis CMOS Cascode amplifier
(Universiti Malaysia Perlis, 2008-03)
The design of CMOS cascode amplier is presented which it will constructed with the circuit of current mirror and two transistor are placed in cascode topology. The design need to achieve the value that will meet the ...
Electrical characterization of 0.15µm CMOS Transistor using TSUPREM-4 and MEDICI
(Universiti Malaysia Perlis, 2008-04)
Physical and electrical characteristics of 0.153m Complementary Metal Oxide Semiconductor (CMOS) were studied. Fabrications of the devices were done by
TSUPREM-4 simulator and electrical characteristics extraction will ...
Coherent effect on LOCOS and STI technique for 0.18 µm CMOS technology using Taurus Workbench
(Universiti Malaysia Perlis, 2008-04)
LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) are two isolation techniques used in integrated circuit fabrication. Further device scaling using
LOCOS technique is no longer practical for technology ...
Electrical characterization of 0.13µm CMOS Transistor using TSUPREM-4 and MEDICI
(Universiti Malaysia Perlis, 2008-04)
Technology CAD (TCAD) refers to the use of computer simulation to model semiconductor
processing and device operation. TCAD has two major functions which are process
simulation and device simulation. It performs the ...
Electrical characterization of 0.13 µm NMOS transistor with Retrograde Well and Halo Implant Structure Respectively
(Universiti Malaysia Perlis, 2008-03)
This project is about the usage of Technology Computer Aided Design (TCAD) in
order to construct NMOS transistor with gate length 0.13 µm. TCAD is use in computer
simulation as process modelling and device operation. ...
Design and analysis of low power using Sleepy Stack and Zig-Zag technique
(Universiti Malaysia Perlis, 2008-04)
Now days the design of CMOS becomes greater where the number of transistor in design increased largely. However there are some problem that occurs during the excellent
design and the increasing of transistor where the ...
The study of the effect of MOS transistor scaling on the critical device parameters
(Universiti Malaysia Perlis, 2007-04)
Since the invention of transistors some 30 years ago, CMOS devices have been scale down aggressively in each technology generations to achieve higher integration density and performance. The device shrinkage allow denser ...