A high speed and well-structured partial product generator for parallel multiplier

Abstract

Previously reported multiplication algorithms mainly focus on rapidly reducing the partial product rows down to final sums and carries used for the final accumulation. In this paper, an efficient approach for partial product generator is presented. The approach focuses on reducing the number of partial product rows by performing the two's complement operation even before applying partial products reduction techniques. Consequently, this directly influences the speed of the multiplication as well as the area of the circuits.