A Divide-by-2 frequency divider design

Abstract

A divide-by-2 frequency divider is presented in this paper. Basic theory and topologies of frequency divider is discussed. The frequency divider is designed for W-CDMA application particularly for demodulator section. It will be used to drive the I/Q mixers. The power consumption of frequency divider is 0.2mA. The circuit is measured with input frequency at 1GHz. All circuits are implemented in fT=45GHz SiGe BiCMOS process.