| dc.contributor.author | Amiza, Rasmi | |
| dc.contributor.author | Uda, Hashim | |
| dc.contributor.author | Awang Mat, Abd F | |
| dc.date.accessioned | 2009-08-13T08:36:18Z | |
| dc.date.available | 2009-08-13T08:36:18Z | |
| dc.date.issued | 2006 | |
| dc.identifier.citation | p.367-372 | en_US |
| dc.identifier.isbn | 0-7803-9730-4 | |
| dc.identifier.uri | http://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4266633 | |
| dc.identifier.uri | http://dspace.unimap.edu.my/123456789/6888 | |
| dc.description | Link to publisher's homepage at http://ieeexplore.ieee.org | en_US |
| dc.description.abstract | One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with lOOnm gate length and 10nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 x 10-9 Watt for fixed current and 3.3565 x 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineering (IEEE) | en_US |
| dc.relation.ispartofseries | Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE 06) | en_US |
| dc.subject | Circuit simulation | en_US |
| dc.subject | Integrated circuits -- Design and construction | en_US |
| dc.subject | Single electron transistors | en_US |
| dc.subject | Transistors | en_US |
| dc.subject | Integrated circuit design | en_US |
| dc.subject | Synopsys TCAD | en_US |
| dc.title | Design of 100nm single-electron transistor (SET) by 2D TCAD simulation | en_US |
| dc.type | Article | en_US |
