Alignment mark architecture effect on alignment signal behavior in advanced lithography

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dc.contributor.author Normah, Ahmad
dc.contributor.author Uda, Hashim
dc.contributor.author Mohd Jeffrey, Manaf
dc.contributor.author Kader Ibrahim, Abdul Wahab
dc.date.accessioned 2009-08-05T09:00:22Z
dc.date.available 2009-08-05T09:00:22Z
dc.date.issued 2006
dc.identifier.citation p.732-739 en_US
dc.identifier.isbn 0-7803-9730-4
dc.identifier.uri http://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4266715
dc.identifier.uri http://hdl.handle.net/123456789/6676
dc.description Link to publisher's homepage at http://ieeexplore.ieee.org en_US
dc.description.abstract The downscaling of CMOS technology becomes a challenge to the scanner alignment system since overlay and alignment accuracy becomes tighter. Such a tight overlay requirement requires a very stable alignment performance. A stable alignment performance is indicates by a stable alignment signal generation. Hence, it is important to perform process characterization in order to choose an alignment mark, which generates the most stable signals. Different alignment mark type may show a different behavior in signal generation. In this paper, the signals behavior will be explored by experimenting using two different alignment mark architecture. This architecture can be further divided into three, which is AH32, AH53, and AH74. Based from the results, AH32 mark shows a significant trend difference between contact and metal mark. This is due to the fact AH32 contact mark is the easiest to be deformed since its feature size is the biggest compared to AH53 and AH74. AH53 and AH74 alignment signal performance between contact and metal mark are comparable. en_US
dc.language.iso en en_US
dc.publisher Institute of Electrical and Electronics Engineering (IEEE) en_US
dc.relation.ispartofseries Proceedings of IEEE International Conference on Semiconductor Electronics (ICSE 2006) en_US
dc.subject Alignment mark en_US
dc.subject Alignment signal en_US
dc.subject Lithography en_US
dc.subject CMOS integrated circuits en_US
dc.subject Metal oxide semiconductors, Complementary en_US
dc.subject Scanner alignment system en_US
dc.title Alignment mark architecture effect on alignment signal behavior in advanced lithography en_US
dc.type Article en_US


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