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Genetic algorithms for VLSI micro-Cell layout area optimization based on binary tree
(ACTA Press, 2008-04-02)
This paper presents a novel module placement based on genetic algorithm (GA) for macro-cell layouts placement that minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized ...
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization
(Institute of Electrical and Electronics Engineering (IEEE), 2008)
Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important ...
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
(Institute of Electrical and Electronics Engineers (IEEE), 2008-05-13)
This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
(Institute of Electrical and Electronics Engineering (IEEE), 2008-05)
This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...