Now showing items 1-2 of 2

    • Alignment mark architecture effect on alignment signal behavior in advanced lithography 

      Normah, Ahmad; Uda, Hashim; Mohd Jeffrey, Manaf; Kader Ibrahim, Abdul Wahab (Institute of Electrical and Electronics Engineering (IEEE), 2006)
      The downscaling of CMOS technology becomes a challenge to the scanner alignment system since overlay and alignment accuracy becomes tighter. Such a tight overlay requirement requires a very stable alignment performance. A ...
    • Design and fabrication of Nanowire-based conductance biosensor using spacer patterning technique 

      Uda, Hashim; Shahrir, Salleh; Siti Fatimah, Abd Rahman; Amir Razif Arief, Jamil Abdullah (Institute of Electrical and Electronics Engineering (IEEE), 2008-12-01)
      Materials have different behaviours and properties at the nanoscales (1-100nm). New theories and discoveries have been found in designing and fabricating at these sizes. Silicon Nanowires has allowed the introduction of ...