Browsing Researchers by Subject "VLIW"

Now showing items 1-2 of 2

    • Implementation of 128/256 bit data bus microprocessor core on FPGA 

      Weng, Fook Lee; Ali Yeon, Md. Shakaff, Prof. Dr. (International Congress for global Science and Technology (ICGST), 2007-05)
      This paper shows the implementation of a large data bus size microprocessor core of 128/256 bits on an Altera Stratix 2 FPGA using a superscalar architecture of 3 parallel pipes with 4 stage pipeline as shown in Figure ...

    • Research of large bit size superscalar pipeline VLIW microprocessor 

      Lee, Weng Fook; Ali Yeon, Md Shakaff (Kolej Universiti Kejuruteraan Utara Malaysia, 2006-06-15)
      A microprocessor’s capability to crunch data is dependent on its bus width. The larger the bus width, the more data it can crunch at any one time. For example, the crunching capability of a 32 bit microprocessor is at a ...