Browsing School of Microelectronic Engineering (FYP) by Subject "Carry Save Adder (CSA)"

Now showing items 1-3 of 3

    • 8-bits X 8-bits modified Booth 1’s complement multiplier 

      Norafiza Salehan (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-05)
      With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination ...

    • High speed six operands 16-bits carry save adder 

      Awatif Hashim (School of Microelectronic Engineering, 2007-03)
      Adders are commonly found in the critical path of many building blocks of microprocessors and digital signal processing chips. The most important for measuring the quality of adder designs in the past were propagation ...

    • Low Power Multiplier Accumulator (MAC) unit using Multiple Threshold CMOS 

      Tang Fhan Thin (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-04)
      Recently, there has been an increasing demand for portable, battery-operated devices like cellular phones and notebook computers. Scaling causes sub-threshold leakage currents to become a large component of total power ...