Low Power Multiplier Accumulator (MAC) unit using Multiple Threshold CMOS

Abstract

Recently, there has been an increasing demand for portable, battery-operated devices like cellular phones and notebook computers. Scaling causes sub-threshold leakage currents to become a large component of total power consumption. Hence, Multiple Threshold CMOS (MTCMOS) has emerged as a promising technique to reduce standby power consumption and extend battery life. There are two divisions for this project. First part is to design the transistor level schematic for whole multiplier accumulator (MAC) unit using Design Architect software. Booth multiplier, Wallace tree multiplication method, carry save adder and carry look ahead adder are used in this project to enhance the design speed in which it is also one of the project objective. Second part is to translate the preceding schematics into layout geometry using IC Station software. The total designed of the MAC unit area consists of 7068 transistors and consumed about 124.8632nW in active mode whereas 110.1263nW merely in standby mode. The optimum power delay product for MAC unit is approximately 0.708fJ. Hence, it proven that this MAC unit design had save up 14.7369nW or 11.8% power consumption during standby mode compared to the active mode by using MTCMOS approach and have also a very high speed performance with 176.37MHz.