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Now showing items 21-27 of 27
Design and analysis of low power using Sleepy Stack and Zig-Zag technique
(Universiti Malaysia Perlis, 2008-04)
Now days the design of CMOS becomes greater where the number of transistor in design increased largely. However there are some problem that occurs during the excellent
design and the increasing of transistor where the ...
High speed six operands 16-bits carry save adder
(School of Microelectronic Engineering, 2007-03)
Adders are commonly found in the critical path of many building blocks of microprocessors and digital signal processing chips. The most important for measuring the quality of adder designs in the past were propagation ...
CMOS Two Stage OP-AMP analysis and design
(Universiti Malaysia Perlis, 2008-03)
The design and analysis CMOS of Two Stage Operational Amplifier that presented has constructed with two basic amplifier which is diffential amplifier and single stage amplifier. The design need to achieve the value that ...
Design a Wideband Low-Noise Amplifier for Wireless Communication using 0.35-µm CMOS Technology
(Universiti Malaysia Perlis, 2007-03)
Low Noise Amplifier (LNA) is one of the receiver front end component. Place near
antenna, this part used to minimize the noise figure of the amplifier while providing enough gain with sufficient linearity to overcome the ...
Synthesis, layout design and simulation of 8-bit Serial Peripheral Interface (SPI) using Leonardo Spectrum and Mentor Graphics tools
(Universiti Malaysia Perlis, 2007)
In this project, Serial Peripheral Interface (SPI), was designed. This project will
include design, synthesis and simulation of SPI. SPI is a synchronous serial data link that operates in full duplex mode and it will ...
Comparison of Speed on 5 Adder Architectures
(Universiti Malaysia Perlis, 2007-05)
Adders are some of the most critical data path circuits in CPU to perform data
processing. The faster the adder, the better it performs data processing. The project
presents a novel of comparison analysis on speed of ...
Simulation for forming Shallow Trench Isolation in the IC using TCAD tools
(Universiti Malaysia Perlis, 2008-04)
A simulation for forming shallow trench isolation (STI) in the integrated circuit
(IC) is introduced. Firstly, using the Taurus Workbench-tools, the first silicon oxide layer and a silicon nitride layer are formed ...