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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hussin, R. | - |
dc.contributor.author | Ali Yeon, Md Shakaff | - |
dc.contributor.author | Idris, N. | - |
dc.contributor.author | Zaliman, Sauli | - |
dc.contributor.author | Ismail, R.C. | - |
dc.contributor.author | Kamarudin, A. | - |
dc.date.accessioned | 2009-08-17T04:25:39Z | - |
dc.date.available | 2009-08-17T04:25:39Z | - |
dc.date.issued | 2007 | - |
dc.identifier.citation | p.54-57 | en_US |
dc.identifier.isbn | 978-0-88986-656-0 (CD) | - |
dc.identifier.uri | http://www.actapress.com/Content_of_Proceeding.aspx?proceedingID=435#pages | - |
dc.identifier.uri | http://dspace.unimap.edu.my/123456789/6905 | - |
dc.description | Link to publisher's homepage at http://www.iasted.org/ | en_US |
dc.description.abstract | In this paper, we attempt to redesign the 4:2 compressors. Since its inception by Weinberger in 1981[1], this concept of compressor has been used in most digital multiplications and multi operand operation scheme. The original of 4:2 compressor has been build using the full adder unit. Hence this compressor is no improvement compare using Wallace tree or other tree structure. Early 90's some designer has modified the 4:2 compressor in order to reduce the critical path. As a result, a worse case to cross a level of 4:2 compressor is 3 XOR [4]. While in this paper, we have redesign 4:2 compressor based on modification of 4:2 compressor [2, 3, 4]. This design has been simulated using Quartus II software to verify the circuit. As a result, total transistor used in our compressor is less 4 than the modified 4:2 compressor and less 2 transistor than the original 4:2 compressor. In term of speed, the critical path of Carry Out signal is same as the original 4:2 compressor. Our compressor is 0.05% faster than modified 4:2 compressor. | en_US |
dc.language.iso | en | en_US |
dc.publisher | International Association of Science and Technology for Development (IASTED) / ACTA Press | en_US |
dc.relation.ispartofseries | Proceedings of the 3rd IASTED International Conference on Advances in Computer Science and Technology, (ACST 2007) | en_US |
dc.subject | Compressor | en_US |
dc.subject | Partial product reduction | en_US |
dc.subject | Booth multiplier | en_US |
dc.subject | Compressor -- Design and construction | en_US |
dc.subject | Algorithms | en_US |
dc.subject | Measurement -- Conversion tables | en_US |
dc.title | Redesign the 4:2 compressor for partial product reduction | en_US |
dc.type | Article | en_US |
Appears in Collections: | School of Computer and Communication Engineering (Articles) Ali Yeon Md Shakaff, Dato' Prof. Dr. |
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