Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/6885
Full metadata record
DC FieldValueLanguage
dc.contributor.authorHasliza, A. Rahim@Samsuddin-
dc.contributor.authorRahman, A. A A-
dc.contributor.authorR. Badlishah, Ahmad-
dc.contributor.authorWan Nur Suryani Firuz, Wan Ariffin-
dc.contributor.authorMuhammad Imran, Ahmad-
dc.date.accessioned2009-08-13T07:43:52Z-
dc.date.available2009-08-13T07:43:52Z-
dc.date.issued2008-
dc.identifier.citationp.207-212en_US
dc.identifier.isbn978-0-7695-3136-6-
dc.identifier.urihttp://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4530477-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/6885-
dc.descriptionLink to publisher's homepage at http://ieeexplore.ieee.orgen_US
dc.description.abstractVery large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of genetic algorithm (GA) techniques for VLSI macro-cell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are simple genetic algorithm (SGA) and steady-state genetic algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuit's data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach (Lin et al., 2002). However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineering (IEEE)en_US
dc.relation.ispartofseriesProceedings of the 2nd Asia International Conference on Modeling & Simulation (AICMS 08)en_US
dc.subjectIntegrated circuit layouten_US
dc.subjectGenetic algorithmsen_US
dc.subjectLogic designen_US
dc.subjectTrees (mathematics)en_US
dc.subjectVery large scale integrated (VLSI)en_US
dc.subjectCircuit optimisationen_US
dc.subjectIntegrated circuitsen_US
dc.subjectIntegrated circuits -- Design and constructionen_US
dc.titleThe performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimizationen_US
dc.typeArticleen_US
Appears in Collections:School of Computer and Communication Engineering (Articles)
R. Badlishah Ahmad, Prof. Ir. Ts. Dr.

Files in This Item:
File Description SizeFormat 
Abstract.pdf8.04 kBAdobe PDFView/Open


Items in UniMAP Library Digital Repository are protected by copyright, with all rights reserved, unless otherwise indicated.