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dc.contributor.authorLee, Weng Fook-
dc.contributor.authorAli Yeon, Md Shakaff-
dc.date.accessioned2009-07-14T04:12:49Z-
dc.date.available2009-07-14T04:12:49Z-
dc.date.issued2008-
dc.identifier.citationAmerican Journal of Applied Sciences , Volume 5, Issue 11, 2008, Pages 1528-1534en_US
dc.identifier.issn1546-9239-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/6437-
dc.description.abstractMicroprocessors have grown tremendously in its computing and data crunching capability since the early days of the invention of a microprocessor. Today, most microprocessors in the market are at 32 bits, while the latest microprocessors from IBM, Intel and AMD are at 64 bits. To further grow the computational capability of a microprocessor, there are two possible paths. One method is to increase the data bus size of the microprocessor to 128/256/512 bits. The larger the data bus size, the more data can be crunched at any one time. The second method is to implement multiple microprocessor core in a single microprocessor unit. For example, Intel's Pentium 4 Dual Core and AMD's Athlon Dual Core both have two microprocessor core within a single microprocessor unit. Latest from Intel and AMD are quad core microprocessors with four microprocessor core within a single microprocessor unit. Both methods have its advantages and disadvantages. Both methods yields different design issues and have different engineering limitations. This research looks into the possibility of implementing a large data bus size VLIW microprocessor core of 256 bits on the data bus. VLIW is chosen as opposed to CISC and RISC due to its ease of scalability.en_US
dc.description.sponsorshipen_US
dc.language.isoenen_US
dc.publisherScience Publications.en_US
dc.subjectLarge data bus size microprocessoren_US
dc.subjectMulticoreen_US
dc.titleImplementing a large data bus VLIW microprocessoren_US
dc.typeArticleen_US
Appears in Collections:School of Computer and Communication Engineering (Articles)
Ali Yeon Md Shakaff, Dato' Prof. Dr.

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