Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication

Abstract

Single-electron transistor (SET) is one of the promising nanotechnologies and distinguished by a very small device size and low power dissipation. This project explains the SET mask design, SET process flow development, and SET process and device simulation. The SET mask design consists of four level masks namely source and drain mask, polysilicon gate mask, contact mask, and metal mask. These masks were designed in nanometer (10-9 m) size using ELPHY Quantum GDS II Editor Software. The source and drain mask is connected by a nanowire placed between source and drain regions. The nanowire is designed with dimension of approximately 100 nm long and 10 nm wide. The process flow which includes the detailed parameters is developed for SET process and device simulation. This process flow consists of ten process modules include wafer cleaning process, material deposition, source/drain and nanowire formation , thermal oxidation, polysilicon deposition, polysilicon gate formation, source/drain implantation, contact formation, metal deposition and formation, and finally annealing and alloying process. The Synopsys TCAD simulation tools are utilized in SET process and device simulation work. The process and device simulation result shows that the single-electron transistor design with a 100 nm length and 10 nm width of the nanowire is working at room temperature (300 K) operation with a capacitance 0.4297 x 10-18F and a charging energy 186.4 meV.