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dc.contributor.authorSharma, Prachi
dc.contributor.authorGupta, Navneet
dc.date.accessioned2017-10-11T03:36:00Z
dc.date.available2017-10-11T03:36:00Z
dc.date.issued2017
dc.identifier.citationInternational Journal of Nanoelectronics and Materials, vol.10 (2), 2017, pages 101-110en_US
dc.identifier.issn1985-5761 (Printed)
dc.identifier.issn1997-4434 (Online)
dc.identifier.urihttp://dspace.unimap.edu.my:80/xmlui/handle/123456789/49933
dc.descriptionLink to publisher's homepage at http://ijneam.unimap.edu.my/en_US
dc.description.abstractIn this paper, we have presented the effect of the density-of-states (DOS) parameters on the performance of n-channel top gated staggered nc-Si TFT. The analysis was performed using ATLAS 2D TCAD simulator from SILVACO. The variation in DOS in nc-Si material and thus on the TFT device performance occurred by altering the channel length and channel quality is presented. The simulation results reveal that the increase in channel length and the degradation in channel quality degrade the trans-conductance and drain current. By iterating the order of parasitic resistance and the value of characteristic decay energy related to material quality, the same trend is achieved for simulated and experimental results for nc- Si TFT with W/L=200μm/50μm.en_US
dc.language.isoenen_US
dc.publisherUniversiti Malaysia Perlis (UniMAP)en_US
dc.subjectNanocrystalline siliconen_US
dc.subjectThin film transistoren_US
dc.subjectTCADen_US
dc.subjectATLASen_US
dc.subjectChannel lengthen_US
dc.subjectDensity of statesen_US
dc.titleTwo dimensional simulation and analysis of density-of-states (DOS) in top-gated nanocrystalline silicon thin film transistor (nc-Si TFT)en_US
dc.typeArticleen_US
dc.contributor.urlprachi.sharma@pilani.bits-pilani.ac.inen_US
dc.contributor.urlngupta@pilani.bits-pilani.ac.inen_US
Appears in Collections:International Journal of Nanoelectronics and Materials (IJNeaM)

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