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http://dspace.unimap.edu.my:80/xmlui/handle/123456789/23993
Title: | Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
Authors: | Mohd Khairuddin, Md Arshad, Dr. Raskin, Jean-Pierre, Prof. Kilchytska, Valeriya, Dr. Andrieu, François, Dr. Scheiblin, Pascal Faynot, O. Flandre, Denis, Prof. mohd.khairuddin@unimap.edu.my jean-pierre.raskin@uclouvain.be pascal.scheiblin@cea.fr |
Keywords: | Drain-induced barrier lowering (DIBL) fully depleted silicon-on-insulator (FDSOI) MOSFETs ultrathin silicon body and thin buried oxide (UTBB) MASTAR model Substrate depletion depth (T Sub) Substrate/buried oxide (BOX) interface space-charge condition Ultrathin silicon body (UTB) |
Issue Date: | Jan-2012 |
Publisher: | Institute of Electrical and Electronics Engineers (IEEE) |
Citation: | IEEE Transactions on Electron Devices, vol. 59 (1), 2012, pages 247-251 |
Abstract: | This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL. |
Description: | Link to publisher's homepage at http://ieeexplore.ieee.org/ |
URI: | ieexplore.ieee.org/xpl/periodicals.jsp http://dspace.unimap.edu.my/123456789/23993 |
ISSN: | 0018-9383 |
Appears in Collections: | School of Microelectronic Engineering (Articles) |
Files in This Item:
File | Description | Size | Format | |
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Extended MASTAR modeling.pdf | 52.87 kB | Adobe PDF | View/Open |
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