Please use this identifier to cite or link to this item:
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/23993
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Mohd Khairuddin, Md Arshad, Dr. | - |
dc.contributor.author | Raskin, Jean-Pierre, Prof. | - |
dc.contributor.author | Kilchytska, Valeriya, Dr. | - |
dc.contributor.author | Andrieu, François, Dr. | - |
dc.contributor.author | Scheiblin, Pascal | - |
dc.contributor.author | Faynot, O. | - |
dc.contributor.author | Flandre, Denis, Prof. | - |
dc.date.accessioned | 2013-03-08T01:50:00Z | - |
dc.date.available | 2013-03-08T01:50:00Z | - |
dc.date.issued | 2012-01 | - |
dc.identifier.citation | IEEE Transactions on Electron Devices, vol. 59 (1), 2012, pages 247-251 | en_US |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | ieexplore.ieee.org/xpl/periodicals.jsp | - |
dc.identifier.uri | http://dspace.unimap.edu.my/123456789/23993 | - |
dc.description | Link to publisher's homepage at http://ieeexplore.ieee.org/ | en_US |
dc.description.abstract | This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.subject | Drain-induced barrier lowering (DIBL) | en_US |
dc.subject | fully depleted silicon-on-insulator (FDSOI) MOSFETs | en_US |
dc.subject | ultrathin silicon body and thin buried oxide (UTBB) | en_US |
dc.subject | MASTAR model | en_US |
dc.subject | Substrate depletion depth (T Sub) | en_US |
dc.subject | Substrate/buried oxide (BOX) interface space-charge condition | en_US |
dc.subject | Ultrathin silicon body (UTB) | en_US |
dc.title | Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs | en_US |
dc.type | Article | en_US |
dc.contributor.url | mohd.khairuddin@unimap.edu.my | en_US |
dc.contributor.url | jean-pierre.raskin@uclouvain.be | en_US |
dc.contributor.url | pascal.scheiblin@cea.fr | en_US |
Appears in Collections: | School of Microelectronic Engineering (Articles) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Extended MASTAR modeling.pdf | 52.87 kB | Adobe PDF | View/Open |
Items in UniMAP Library Digital Repository are protected by copyright, with all rights reserved, unless otherwise indicated.