Low Power Multiplier Accumulator (MAC) unit using Sleepy Stack technique

Abstract

The main objective of this project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, the focus is on leakage power reduction. In this project, a novel circuit structure called “sleepy stack” is presented. The sleepy stack is a combination of two well known low-leakage techniques which are the forced stack technique and the sleep transistor technique. By combining two prior techniques, however, the sleepy stack technique can achieve ultra-low leakage power consumption while saving state. Since the sleepy stack technique comes with a huge area compared to a conventional Complementary Metal Oxide Semiconductor (CMOS) technique, the sleepy stack technique can be applicable to a design that requires ultra-low leakage power consumption with quick response time and is able to pay the associated area cost. There are two divisions for this project. First part is to design the MAC unit using Quartus II. Then the design is drawn in transistor level schematic using Design Architect software. Booth multiplier, Wallace tree multiplication method, carry save adder and carry look ahead adder are used in this project to enhance the design speed. The total designed of the MAC unit area consists of 29,547 transistors and consumed about 119.3083nW in active mode whereas 75.7775nW merely in sleep mode. Hence, it proven that this MAC unit design had saved up to 45.5308nW power consumption during sleep mode compared to the active mode by using Sleepy Stack approach.