High speed six operands 16-bits carry save adder

Abstract

Adders are commonly found in the critical path of many building blocks of microprocessors and digital signal processing chips. The most important for measuring the quality of adder designs in the past were propagation delay, and area. The purpose of the project is to implement a high-speed three levels six operands of 16-bits CSA with RCA at the end of the design. The objective of this project are design faster execution of CSA using gate logic design and implement it to the Altera UP2 board. The project is simulated and clarifies the output using Quartus II software and Altera UP2 board implementation to verify the design architectures. The high-speed circuit was designed by using smallest delay between five different logic gates Full Adder (FA) and by adding pipeline. This project has been achieved from 16.84MHz to the 90.09MHz speed on EPF10K70RC240-4 device. This result contribute CSA is in faster speed.