Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/11392
Full metadata record
DC FieldValueLanguage
dc.contributor.authorWeng, Fook Lee-
dc.contributor.authorAli Yeon, Md. Shakaff, Prof. Dr.-
dc.date.accessioned2011-03-23T08:58:59Z-
dc.date.available2011-03-23T08:58:59Z-
dc.date.issued2007-05-
dc.identifier.citationJournal of Programmable Devices, Circuits, and Systems, vol.7(1), 2007, pages 7-13en_US
dc.identifier.urihttp://www.icgst.com/pdcs/Volume7/Issue1/PDCS0712001.pdf-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/11392-
dc.descriptionLink to publisher's homepage at http://www.icgst.comen_US
dc.description.abstractThis paper shows the implementation of a large data bus size microprocessor core of 128/256 bits on an Altera Stratix 2 FPGA using a superscalar architecture of 3 parallel pipes with 4 stage pipeline as shown in Figure 1. The system level implementation utilizing the implemented microprocessor core on FPGA is shown in Figure 2. The micro-architecture of the microprocessor core architecture of Figure 1 is implemented using four pipe stages of fetch, decode, execute and writeback with a shared register file for all 3 parallel pipes, as shown in Figure 3.en_US
dc.language.isoenen_US
dc.publisherInternational Congress for global Science and Technology (ICGST)en_US
dc.subjectLarge data bus size microprocessoren_US
dc.subjectVLIWen_US
dc.subjectFPGAen_US
dc.titleImplementation of 128/256 bit data bus microprocessor core on FPGAen_US
dc.typeArticleen_US
dc.contributor.urlseanlee@emersysdesign.comen_US
dc.contributor.urlaliyeon@unimap.edu.myen_US
Appears in Collections:School of Mechatronic Engineering (Articles)
Ali Yeon Md Shakaff, Dato' Prof. Dr.

Files in This Item:
File Description SizeFormat 
doc4.pdf654.98 kBAdobe PDFView/Open


Items in UniMAP Library Digital Repository are protected by copyright, with all rights reserved, unless otherwise indicated.