Browsing School of Computer and Communication Engineering (Articles) by Subject "Trees (mathematics)"
Now showing items 1-3 of 3
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A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
(Institute of Electrical and Electronics Engineering (IEEE), 2008-05)This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ... -
Improved booth encoding for reduced area multiplier
(Institute of Electrical and Electronics Engineering (IEEE), 2006-12)In designing high density circuit, size is a major concern in design. This paper presents a simple modification to the Booth Multiplier that can effectively reduce the area with an accepted scarified in speed. A conventional ... -
The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization
(Institute of Electrical and Electronics Engineering (IEEE), 2008)Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important ...