| dc.contributor.author | Mohd Khairuddin, Md Arshad, Dr. | |
| dc.contributor.author | Uda, Hashim, Prof. Dr. | |
| dc.contributor.author | Noraini, Othman | |
| dc.date.accessioned | 2014-09-02T08:25:47Z | |
| dc.date.available | 2014-09-02T08:25:47Z | |
| dc.date.issued | 2014-05 | |
| dc.identifier.uri | http://dspace.unimap.edu.my:80/dspace/handle/123456789/37037 | |
| dc.description | Received a Gold medal and in 25th International Invention, Innovation & Technology Exhibition (ITEX'14), 8th-10th May at Kuala Lumpur Convention Centre. | en_US |
| dc.description.abstract | Fully-depletion operation is mandatory requirement for ultra-scaled devices (Le. < 45 nm technology) which only can be achieved either multi-gate (Le. FinFET) or thin body Silicon-on-Insulator (SOl). Thin body SOl offers another interesting feature compared to any other
technologies i.e. back-gate biasing. In this invention, we utilize asymmetrical contact from the top which provide improved performance and better controlled of short-channel effects in thin body and thin buried oxide of SOl MOSFETs. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Universiti Malaysia Perlis (UniMAP) | en_US |
| dc.relation.ispartofseries | 25th International Invention, Innovation & Technology Exhibition;;ITEX'14 | |
| dc.subject | International Invention, Innovation & Technology Exhibition (ITEX'14) | en_US |
| dc.subject | Silicon-on-Insulator (SOl) | en_US |
| dc.subject | SOl MOSFETs | en_US |
| dc.subject | Research and innovation | en_US |
| dc.title | Asymmetrical Double Gate: significant improvement in ultra-scaled sol mosfet | en_US |
| dc.type | Other | en_US |
| dc.publisher.department | Institute of Nano Engineering Electronic | en_US |
| dc.contributor.url | mohd.khairuddin@unimap.edu.my | en_US |
