Design and analysis of Floating Point divider

Abstract

As the advances of VLSI technology, low power design has become an important topic in VLSI design. Scaling down supply voltage is an effective way for power reduction because of its quadratic relationship to dynamic power. The objective of this project is to design and analysis of floating point divider using Mentor Graphics tools. Mentor Graphics is an Electronic Design Automation (EDA) package. The suite of tools can handle anything from Printed Circuit Board (PCB) to Hardware Description Language(HDL). In the circuit design area, there are tools for schematic capture, digital and analog simulation, physical layout, and design verification. Many libraries contain models for popular existing design components. Floating-point divider is generally regarded as a low frequency and high latency operation in typical floating-point applications. For analysis purposes, the simulation results have been compared in terms of power consumption, delay, speed, power delay product (PDP) and layout area. Lower PDP meaning that the power is better translated into speed of operation. Floating point divider circuit consumes power is 195mWatt at 10 million operations per second. Floating point divider circuit produces 5ns delay time and 200MHz in speed. For PDP, floating point divider circuit operates 0.975ns at 10 million per second.