Coherent effect on LOCOS and STI technique for 0.18 µm CMOS technology using Taurus Workbench

Abstract

LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) are two isolation techniques used in integrated circuit fabrication. Further device scaling using LOCOS technique is no longer practical for technology generations below 0.35 µm. STI technique was thus introduced because of its ability to maintain sufficient oxide thickness. Many problems of defective devices in silicon integrated circuits can be ultimately traced to stresses that develop at various stages of integrated circuit fabrication. Due to the current state of affairs, this project is aimed at studying the effects of stress present in LOCOS isolation technique and STI technique. Research is focused on the design of CMOS (Complementary Metal Oxide Semiconductor) transistor with 0.18 µm technology. Fabrication and simulation of the CMOS transistor is done using virtual wafer fabrication software, Taurus Workbench. Device simulation involves two types of tools namely TSuprem-4 (fabrication process) and Medici(electrical properties). Based on stress plot produced, its show that STI technique produces a lower stress level compared to LOCOS isolation technique. Likewise, STI technique results in lower sheet resistance in LDD structures giving 235.0 ohm/sq for nMOS and 2.3 x 108 ohm/sq for pMOS. Threshold voltage extracted from STI simulation records 2.4 V for nMOS and -0.4 V for pMOS. Coherent effect (especially stress effect) has been recognized as the one of the factors that responsible for the oxide diminishing phenomenon which leads to damaging the plane and producing crack. In view of this, the use of STI technique in sub-micron devices is further substantiated.