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dc.contributor.authorFarid, Ghani, Prof. Dr.
dc.contributor.authorAbid, Yahya, Dr.
dc.contributor.authorAbdul Kader
dc.date.accessioned2011-10-28T07:36:54Z
dc.date.available2011-10-28T07:36:54Z
dc.date.issued2011-02-20
dc.identifier.citationp. 206-210en_US
dc.identifier.isbn978-1-6128-4690-3
dc.identifier.urihttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5958912
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/15124
dc.descriptionLink to publisher's homepage at http://ieeexplore.ieee.orgen_US
dc.description.abstractThis paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.ispartofseriesProceedings of the IEEE Symposium on Computers and Informatics (ISCI 2011)en_US
dc.subjectBit error rateen_US
dc.subjectCommunication channelsen_US
dc.subjectEncodingen_US
dc.subjectFPGAen_US
dc.subjectQC-LDPCen_US
dc.subjectRayleigh Fadingen_US
dc.titleNew QC-LDPC codes implementation on FPGA platform in Rayleigh fading environmenten_US
dc.typeWorking Paperen_US
dc.contributor.urlfaridghani@rediffmail.comen_US
dc.contributor.urlabidusm@gmail.comen_US
dc.contributor.urlkdr2k4@yahoo.comen_US


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