The design of an encryption chip using vigenère cipher

Abstract

This project proposes a hardware implementation of a modified Vigenère cipher algorithm. The modified Vigenère algorithm comprises of a diffused plaintext encrypted with a pseudorandom session key generator symmetrically. The master key then is encrypted using asymmetric encryption technique. The combination of symmetric and asymmetric encryption algorithm achieves security of the message and the key during transfer to the receiver. The design is written in synthesizable Verilog HDL code and the ciphertext is verified through decryption of itself to obtain the original message. The hardware resource consumes 3,215 LEs on an Altera CycloneII FPGA chip and operates at 10.76 MHz.