Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities

Abstract

The Micro Fabrication Cleanroom in University Malaysia Perlis (UniMAp) was completed in December 2003 and was built as a teaching laboratory. The goal of this project is to simulate a 0.35um negative-metal-oxide-semiconductor (NMOS) process based on UniMAP cleanroom facilities and to study the feasibility of adopting this process using cleanroom facilities. The result of the simulation will be compared with UC Berkeley 0.35um process design in terms of the Id-Vgs characteristic. NMOS transistor will be simulated using TCAD tools that consist of Taurus TSUPREM-4 for process simulation and Taurus Medici for the device simulation. The simulation is run for UC Berkeley 0.35 nMOS transistor and the second process simulation is for 0.35 um NMOS that can fabricate in UniMAP Micro Fabrication cleanroom. For nMOS 0.35 um in UniMAP Micro Fabrication cleanroom consists of four module based on design and fabricate mask that consist four step mask layout that is source drain formation, gate formation, contact formation and metallization. The voltage threshold for UniMAP 0.35um NMOS transistor is 0.25 volts. The voltage threshold for typical NMOS process is 0.3 volts. Material parameters that effect voltage threshold, Vt includes the gate conductor material, the channel doping concentrations, the gate insulation material (SiO2) and the thickness of the gate material.