Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
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Date
2023-01Author
Izwanizam, Yahaya
F. Salehuddin
K. E. Kaharudin
A. H. Afifah Maheran
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This paper describes the virtual design of a 22nm gate length p-type metal oxide
semiconductor, PMOS. Silvaco, TCAD tools were used to fabricate the device design and to
characterize the device’s electrical properties. Fixed field scaling rules are applied to obtain
the transistor’s electrical parameters set by ITRS 2013. In order to take the challenges that
arise in the fabrication of nano-sized transistors and enhance their performance, advanced
and novel technologies are applied. Using the statistical modelling of L9 Taguchi
methodology, the development process is primarily focused on the tool's edge voltage. Four
parameters have been divided into three distinct steps in order to conduct nine different
experiments. The final confirmation result indicates that VTH is closer to the nominal value
-0.206V following optimization techniques. This matches the ITRS 2013 requirements for
high performance. This paper examines the design of a p-MOS double gate containing a layer
of graphene as it is known to have a high mobility value