Showing items related by title, author, creator and subject.

• A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

  Hasliza, A. Rahim@Samsuddin; Ab Rahman, A. A H; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin (Institute of Electrical and Electronics Engineering (IEEE), 2008-05)

  This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...

• The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization 

  Hasliza, A. Rahim@Samsuddin; Rahman, A. A A; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin; Muhammad Imran, Ahmad (Institute of Electrical and Electronics Engineering (IEEE), 2008)

  Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important ...

• USM pertama lantik CIO 

  Faridzwan, Abdul Ghafar (Berita Harian, 2012-07-21)