Now showing items 1-2 of 2

    • Alignment mark architecture effect on alignment signal behavior in advanced lithography 

      Normah, Ahmad; Uda, Hashim; Mohd Jeffrey, Manaf; Kader Ibrahim, Abdul Wahab (Institute of Electrical and Electronics Engineering (IEEE), 2006)
      The downscaling of CMOS technology becomes a challenge to the scanner alignment system since overlay and alignment accuracy becomes tighter. Such a tight overlay requirement requires a very stable alignment performance. A ...
    • Borophosphosilicate glass (BPSG) reflow characterization for submicron CMOS technology 

      Uda, Hashim; Ramzan, Mat Ayub; Nik Hazura, Nik Hamat (Universiti Kebangsaan Malaysia, 2007)
      This paper involves the planarization of borophosphosilicate glass (BPSG) film using a new recipe for annealing process to improve the borophosphosilicate glass (BPSG) film flatness after reflow. This improvement is for ...