Now showing items 1-8 of 8

    • 8-bits X 8-bits modified Booth 1’s complement multiplier 

      Norafiza Salehan (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-05)
      With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination ...
    • Design and analysis of low power using Sleepy Stack and Zig-Zag technique 

      Wan Nurul Liyana Wan Zulkefle (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2008-04)
      Now days the design of CMOS becomes greater where the number of transistor in design increased largely. However there are some problem that occurs during the excellent design and the increasing of transistor where the ...
    • Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications 

      Mohd Nazri Md Rejab (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2008-04)
      A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially ...
    • Design of Control Circuit for an Inverter 

      Nurfaiza Hanim Mohd Saleh (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-04)
      This thesis develops sinusoidal pulse width modulation (SPWM) technique switching for single phase bridge inverter. This technique is design using (VHDL) programming with Altera Quartus II environment. A general framework ...
    • The Effect of Process Parameters on Metal Step Coverage for Aluminum by Evaporation Technique 

      Noraishah Azman (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-03)
      The degree to which deposited metals cover steps over topography is important to the yield and reliability of devices in very large scale integrations (VLSI). In evaporated and sputtered thin films, the most difficult steps ...
    • Gate Oxide Integrity (GOI) Characterization For Deep Submicron CMOS Device 

      Norain Mohd Saad (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-03)
      Since the early days of Very Large Scale Integration (VLSI) era, the scaling of gate oxide thickness has been instrumental in controlling the short channel related effects in state-of-the-art device structure, as MOS gate ...
    • Low Power Multiplier Accumulator (MAC) unit using Sleepy Stack technique 

      Aaron Selvam Thangamany (Universiti Malaysia PerlisSchool Of Microelectronic Engineering, 2008-05)
      The main objective of this project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, the focus is on leakage power reduction. In this project, a novel circuit structure ...
    • Ultra low power 8-bit microcontroller using Super Cut-Off CMOS (SCCMOS) 

      Sa Nuth Nai Chuan (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-04)
      As the advances of VLSI technology, low power design has become an important topic in VLSI design. Scaling down supply voltage is an effective way for power reduction because of its quadratic relationship to dynamic ...