A Divide-by-2 frequency divider design

dc.contributor.author	A., Marzuki
dc.contributor.author	Tun Zainal Azni, Zulkifli
dc.contributor.author	Basir, Saibon
dc.date.accessioned	2009-08-24T01:53:41Z
dc.date.available	2009-08-24T01:53:41Z
dc.date.issued	2005-05-18
dc.identifier.citation	p.19-22	en_US
dc.identifier.uri	http://dspace.unimap.edu.my/123456789/7041
dc.description	Organized by Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM), 18th - 19th May 2005 at Putra Palace Hotel, Kangar.	en_US
dc.description.abstract	A divide-by-2 frequency divider is presented in this paper. Basic theory and topologies of frequency divider is discussed. The frequency divider is designed for W-CDMA application particularly for demodulator section. It will be used to drive the I/Q mixers. The power consumption of frequency divider is 0.2mA. The circuit is measured with input frequency at 1GHz. All circuits are implemented in fT=45GHz SiGe BiCMOS process.	en_US
dc.language.iso	en	en_US
dc.publisher	Kolej Universiti Kejuruteraan Utara Malaysia	en_US
dc.relation.ispartofseries	Proceedings of the 1st National Conference on Electronic Design	en_US
dc.subject	Frequency dividers	en_US
dc.subject	Oscillators, Crystal	en_US
dc.subject	Frequency dividers -- Design and construction	en_US
dc.subject	Metal oxide semiconductors, Complementary	en_US
dc.subject	Integrated circuits	en_US
dc.title	A Divide-by-2 frequency divider design	en_US
dc.type	Working Paper	en_US