Now showing items 174-185 of 185

    • Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit 

      Kilchytska, Valeria I.; Mohd Khairuddin, Md Arshad; Makovejev, Sergej; Olsen, Sarah H.; Andrieu, Francois; Poiroux, Thierry; Faynot, Olivier; Raskin, Jean Pierre; Flandre, Denis (Elsevier Ltd., 2012-04)
      In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender ...
    • Under Bump Metallurgy (UBM)-a technology review for flip chip packaging 

      Mohd Khairuddin Md Arshad; Uda Hashim; Muzamir Isa (Department of Mechanical Engineering, University Malaya, 2007)
      Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size ...
    • Uninterruptible power supply monitoring system with Visual Basic 

      Sohiful Anuar, Zainol Murad; Mohd Nazrin, Md Isa; Norazeani, Abdul Rahman (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2006-12-29)
      In industrial process today, reliability of equipment is very important. Power supply must be able to cater the need of industrial process. In case of power failure, backup power supply system must be able to support the ...
    • UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime 

      Mohd Khairuddin, Md. Arshad; Makovejev, Sergej; Olsen, Sarah H.; Andrieu, F.; Raskin, Jean Pierre; Flandre, Denis; Kilchytska, Valeriya I. (Elsevier Ltd., 2013)
      In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations ...
    • Velocity profile investigation of FFS microchannel at Re 100 

      Retnasamy, Vithyacharan; Zaliman, Sauli, Dr.; Taniselass, Steven; Nor Shakirina, Nadzri; Hsio Mei, Tan; Khairul Anwar, Mohamad Khazali; Nooraihan, Abdullah (Trans Tech Publications, 2014)
      Recently, microfluidics system has been widely employed in various areas for instance biomedical,pharmaceuticals and cell biological researchdue to its advantages. The flow behavior in microchannels with different ...
    • A voltage reference circuit for current source of RFIC blocks 

      Marzuki, Arjuna; Zaliman, Sauli; Ali Yeon, Md Shakaff (Emerald Group Publishing Limited, 2008)
      Purpose - The purpose of this paper is to design a voltage reference circuit for current source of radio frequency integrated circuit blocks. The voltage reference circuit is called voltage for current source (VCS). ...
    • Wettability analysis on platinum deposited wafer after reactive ion ecthing using SF6+argon/CF4+argon gaseous 

      Retnasamy, Vithyacharan; Zaliman, Sauli, Dr.; Aaron, Koay Terr Yeow; Goh, Siew Chui; Kamarudin, Hussin, Brig. Jen. Dato' Prof. Dr. (AENSI Publisher All rights reserved, 2013-10)
      Wettability in microfluidic has direct influence to its fluid flow channels. This paper investigates the variable parameters that affect the wetability in terms of contact angle on a Platinum deposited wafer after reactive ...
    • Wettability and surface roughness study on RIE treated aluminium deposited surface 

      Retnasamy, Vithyacharan; Zaliman, Sauli, Dr.; Uda, Hashim, Prof. Dr.; Palianysamy, Moganraj; Aaron, Koay Terr Yeow; Ramzan, Mat Ayub (Trans Tech Publications, 2014-04)
      Design of Experiment (DOE) is a technique for optimizing process which has controllable inputs and measurable outputs. As a method of DOE, 24 Full Factorial design is used to study the effect of Reactive Ion Etch towards ...
    • Wire bond shear test simulation on hemispherical surface bond pad 

      Zaliman, Sauli, Dr.; Retnasamy, Vithyacharan; Wan Mokhzani, Wan Norhaimi; Johari, Adnan, Assc. Prof. Dr.; Palianysamy, Moganraj (Trans Tech Publications, 2012-12)
      Wire bonding process is an interconnection method adopted in the semiconductor packaging manufactory. One of the method used to assess the reliability and bond strength of the bonded wires are wire bond shear test .In this ...
    • Wire bond shear test simulation on sharp groove surface bond pad 

      Zaliman, Sauli, Dr.; Retnasamy, Vithyacharan; Taniselass, Steven; Ahmad Husni, Mohd Shapri; Vairavan, Rajendaran (Trans Tech Publications, 2012-12)
      Wire bonding process is first level interconnection technology used in the semiconductor packaging industry. The wire bond shear tests are used in the industry to examine the bond strength and reliability of the bonded ...
    • WSS investigation in microfluidic FFS channel at Re 500 

      Zaliman, Sauli, Dr.; Retnasamy, Vithyacharan; Taniselass, Steven; Nor Shakirina, Nadzri; Hsio Mei, Tan; Khairul Anwar, Mohamad Khazali; Nooraihan, Abdullah (Trans Tech Publications, 2014-01)
      Wall shear stress (WSS) is one of the important variables in microfluidic devices. In this paper WSS distribution for a microfluidic device in Forward Facing Step (FFS) configuration has been investigated using Reynolds ...
    • ZnO photoanode effect on the efficiency performance of organic based dye sensitized solar cell 

      Ili Salwani, Mohamad; S S, Ismail; ‪Mohd Natashah, Norizan; ‪Sohiful Anuar, Zainol Murad‬; Mohd Mustafa Al Bakri, Abdullah (IOP Publishing Ltd, 2017-06)
      Dye sensitized solar cell has been emerged as one of the most promising candidates for photovoltaics applications in good quality of their low manufacturing cost and impressive conversion energy. Titanium dioxide (TiO₂) ...