Now showing items 1-2 of 2

    • A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Al-Hadi, Ab Rahman; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Arrifin (Institute of Electrical and Electronics Engineers (IEEE), 2008-05-13)
      This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...
    • A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Rahman, A. A H; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Ariffin (Institute of Electrical and Electronics Engineering (IEEE), 2008-05)
      This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...