Design and analysis of low power using Sleepy Stack and Zig-Zag technique

Abstract

Now days the design of CMOS becomes greater where the number of transistor in design increased largely. However there are some problem that occurs during the excellent design and the increasing of transistor where the leakage power also increased. Furthermore, the leakage power that occurs makes the design not efficiency and not practical. As the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically (indeed, even exponentially) in nano scale silicon VLSI technology, the importance of reducing leakage power consumption cannot be overstressed. To solve this problem there are many types of technique of designing the VLSI CMOS appear where the mainly objective is to reducing the leakage power that occurs and achieve the higher performance in terms of speed, delay and power consumption. The sleepy stack technique and zig-zag technique can be used to reduce the leakage power that occurs. The voltage scaling is used where the supply voltage that used is lower to achieve the low power design. In this project concerns on designing 8 bit of ALU, PC and IR using these techniques. Then, from the generated waveform, the delay, speed, area, power consumption and power delay product (PDP) can be determined. From these results the analysis and comparison the performance between both techniques can be done. In sleepy stack technique, the number of transistors that used is more than 60% compared with the zig-zag technique. Sleepy stack Technique produces higher delay than zig-zag technique where total delay for sleepy stack circuit is 135.0ns and the other is 85.0ns.