Study in Design of 32 X 4Bit Static Random Access Memory (SRAM)

Abstract

Study in design Static Random Access Memory (SRAM) using Mentor Graphic and simulation process with Eldo simulator. The research made on the operation of six transistors, its advantage over Dynamic Random Access Memory (DRAM) and circuit’s architecture. The design and simulation process prepared for all the internal components in SRAM which finalized with the combination schematic. Comparison performed for every simulation based on the theoretical in digital logic and the waveform performance. This project have four procedure which were creating the schematic of the circuit, creating symbol of the schematic, creating testbench for electrical testing and analog simulation which produce the output in voltage form. Result produced in the final design which a combination of internal components not successful and same as the expected which can deliver read and write operation. The failure occurs may cause of the inappropriate connection in the combination circuits, the declaration of signal in testbench which not suitable for the high number of input and output signals. This situation must be cause of the unsatisfactory supporting circuits for ensuring the six transistors can perform the SRAM operation. Although the final design does not produce the desired output, four of the objectives accomplished successfully. Recommendation in this project for future was an improvement that can be made in the experimental design with the specified objectives.