Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics

Abstract

In this project the main topology of two bit adder including the most interesting of those recently proposed, are compared for delay, power dissipation, area and power delay product (PDP) . The comparison has been performed for 2 bit adder using Mirror Adder,Dynamic Adder and Pipelined Adder configuration, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power- delay product. The investigation has been carried out with properly defined simulation runs on a Mentor Graphic environment using 0.35μ tsmc technology.The design guidelines have been derived to select the most suitable topology for the design features required. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, expect for short chains of blocks or for cases where minimum power consumption is desired, topologies with transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS and other topologies. For analysis, pipelined is absolute have a great speed between others adders and suitable use for high-power. For speed, that compares which adder has a lowest delay according to waveform. For power dissipation, result exists in file (.chi) from test bench and power delay product out come from power dissipation multiply with delay.