Stable 2 Stage CMOS Amplifier

Abstract

In the last few years there has been an effort to integrate electrochemical instrumentation. A critical component of such a system is an amplifier. These projects design a “Stable Two stage CMOS amplifier”. This is achieved through the use of an optimized cascaded compensation topology. A new shifting technique allows independent optimization of drive capability, noise and systematic offset voltage. The circuit is in a 0.35μm technology and has a quiescent current consumption of 110μA. This designing currently using Mentor Graphic software to test the schematic and also to design the layout. The design layout is designed using rules from TSMC. Using cascoded compensation with optimized circuit parameters, the worst case phase margin of the amplifier can be controlled to acceptable values. In two stage CMOS amplifier, there is usually a tradeoff aware high output drive capability and low systematic offset voltage. The output voltage that expects to get must in stable conditional and the bias current setting according to the calculation estimation.